1. Field of the Invention
The present invention relates to a clock regenerator. More particularly, in a digital radio transmission system to which PSK (Phase Shift Keying) is applied between a sending digital radio apparatus and a receiving digital radio apparatus, the present invention relates to a clock regenerator applicable to a receiving digital radio apparatus suitable for clock regeneration regardless of frequency error amount (predetermined phase error amount) between a carrier received from the sending digital radio apparatus and a carrier generated in the receiving digital radio apparatus.
2. Description of the Background Art
FIG. 5 shows an example of the functional block of a conventional clock regenerator used in a receiving digital radio apparatus in a digital radio transmission system to which π/4 shift QPSK (Quadrature Phase Shift Keying) is applied between a sending digital radio apparatus and a receiving digital radio apparatus.
The clock regenerator shown in FIG. 5 comprises a phase detector 50, a differential detector 56 composed of a one-symbol delay 52 and a differential circuit 54, a clock regenerator 58, a phase corrector 60, and a phase decision circuit 62. As shown in FIG. 5, the phase detector 50, differential detector 56, and clock regenerator 58 are used in the conventional clock regenerator shown in FIG. 5.
More specifically, as shown in FIG. 5, the conventional clock regenerator uses the phase difference information (differential detection information) generated based on the difference in phase between the current symbol and the immediately-preceding symbol to regenerate or recover clocks.
The operation of the clock regenerator shown in FIG. 5 will be described. The phase detector 50 receives, at its input 200, quadrature detection signals R(t)=IR(t),QR(t), where t is time, the base-band signals generated by quadrature-detecting the received signals. The received analog signals IR(t) and QR(t) are each input to the A/D converters, not shown in the figure, in the phase detector 50. These A/D converters convert the signals to digital i and q signals.
The converted digital signals i and q are input to the tan−1 (q/i) operation circuit, not shown in the figure, in the phase detector 50. The digital signals are converted to tan−1 (q/i) and then to phase information A(t) by this tan−1 (q/i) operation circuit. In the A/D converters described above, the signals are A/D converted at the symbol rate synchronizing with the reception symbol timing signal.
The phase signal A(t) generated by the phase detector 50 is sent to one of the two inputs of the differential circuit 54 on a signal line 202 and to the input of the one-symbol delay 52. The one-symbol delay 52 delays the received phase signal A(t) for one symbol period to generate a one-symbol-delayed phase signal A(t−T), where T is a one-symbol period.
The phase signal A(t−T) generated by the one-symbol delay 52 is input to the other input of the differential circuit 54 on a signal line 204. The differential circuit 54 generates the phase difference between the one-symbol-delayed signal A(t−T) and the received phase signal A(t).
More specifically, from an output 206 and an output 208 of the differential circuit 54, the phase difference information, that is, the phase deviation information AT(t)=A(t−T)−A(t) is output. This phase deviation information AT(t) is sent to the phase corrector 60 on the signal line 206. The phase corrector 60 changes the phase deviation information AT(t) into an absolute phase. The phase deviation information AT(t) which has been changed into an absolute phase is sent to the phase decision circuit 62 on a signal line 210. The phase decision circuit 62 also receives the symbol timing signal (clock signal) from the clock regenerator 58 on a signal line 214.
The phase decision circuit 62 estimates the transmission phase difference based on the phase deviation information AT(t), which has been sent from the phase decision circuit 62 changed into an absolute phase, and on the symbol timing signal 214 and demodulates the signal to the data that was sent (in this example, 2-bit data). The data demodulated by this circuit is output to a signal line 212.
The phase deviation information AT(t)=A(t−T)−A(t) generated by the differential circuit 54 described above is sent also to the clock regenerator 58 on the signal line 208. The clock regenerator 58 extracts the phase extraction timing signal, that is, the symbol timing signal, from the received phase deviation information AT(t), and regenerates or recovers the clock signal, which synchronizes with this symbol timing signal, from the extracted symbol timing signal. The regenerated clock signal is sent to signal lines 214 and 216.
In this example, the differential circuit 54 subtracts the phase signal A(t) of the immediately-preceding symbol of a one-symbol-delayed phase signal from the one-symbol-delayed phase signal A(t−T). The differential circuit may also subtract the one-symbol-delayed phase signal A(t−T) of a symbol from the phase signal A(t) of the symbol.
The basic operation of the configuration shown in FIG. 5 was described above. The operation of the configuration shown in FIG. 5 will be described more in detail with a preamble pattern, from which the symbol timing signal is easily extracted, as an example.
In such a transmission system, the sending side appends an easily extractable preamble pattern near the start of a sending frame for quick timing signal extraction. In this example, this easily extractable preamble pattern “011001100110. . . ” is used. FIG. 6 shows the phase transition of the preamble pattern described above. The phase transition information in FIG. 6 corresponds to the output information from the phase detector 50.
FIG. 7 shows phase transition information on two preamble patterns with the horizontal axis as the time axis. One is phase transition information on the preamble pattern before the one-symbol-delay as plotted with a solid line 401, and the other is phase transition information on the preamble pattern generated by delaying the preamble pattern before the one-symbol-delay for the one-symbol period as plotted with a solid line 403. The former information 401 corresponds to the output information of the phase detector 50, while the latter information 403 to the output information of the one-symbol delay 52.
FIG. 8 shows the phase transition (differential detection) of the preamble pattern 405 that is the difference between the phase transition of the one-symbol-delayed preamble pattern and the phase transition of the preamble pattern before the one-symbol delay. The phase transition 405 corresponds to the output information from the differential circuit 54.
As understood from FIG. 8, the output information of the differential circuit 54 obtained from the preamble pattern is a cyclic or periodic wave with the amplitude of π. The differential circuit 54 sends this cyclic wave with the amplitude of π to the clock regenerator 58. The clock regenerator 58 counts the number of periods T/2 in respect of crossing the center of the amplitude (π/4) of the cyclic wave sent from the clock regenerator 58 to generate the phase extraction timing signal, that is, the symbol timing signal. The circuit generates the clock signal synchronizing with the extracted symbol timing signal.
Actually, however, a carrier frequency phase error is involved between the carrier (transmission frequency) of the sending digital radio apparatus and the carrier of a receiving digital radio apparatus. Therefore, the receiver side finds out a phase error in the carrier frequency. Suppose that the phase error in the carrier frequency is α+θ×t, where α and θ are constants. Let AT(t)1 be the phase deviation information including this phase error. Then, the phase deviation information AT(t)1 output from the differential circuit 54 is represented by expression (1) as follows:AT(t)1=(A(t−T)+α+θ(t−T))−(A(t)+α+(θ×t)) =A(t−T)−A(t)+θ1  (1)Because θ1=−θ×T where T is a one-symbol time, θ1=−θ is a phase deviation error caused by the carrier frequency error between the sending digital radio apparatus and the receiving digital radio apparatus. Note that θ1 may be represented in radians.
The phase deviation information including the phase deviation error θ1 is sent to the clock regenerator 58. Therefore, the symbol timing signal generated by the clock regenerator 58 includes the symbol timing error such as the one shown in FIG. 9.
As described above, phase deviation information generated by the conventional clock regenerator shown in FIG. 5 includes a phase deviation error θ1. This error prevents the clock regenerator from regenerating symbol clocks correctly and from regenerating demodulated data correctly.